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Envelope-to: pamay@sapasequipment.com
Delivery-date: Mon, 18 Sep 2023 11:27:29 -0400
Date: Mon, 18 Sep 2023 11:26:32 -0400 (EDT)
From: GlobalSpec Webinars <reply@email.globalspec.com>
To: pamay@sapasequipment.com
Message-ID: <20230918112632.32747981.487221@sailthru.com>
Subject: Webinar: Partitioning Designs into Multiple FPGAs with Veloce
 proFPGA Prototyping Solution
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<span style="font-size:16px; line-height:28px; font-family:'Open Sans', Arial, sans-serif !important;">Join us for a webinar</span><br />
<span style="font-size:34px; font-weight:600; font-family:'Open Sans', Arial, sans-serif !important;">Partitioning Designs into Multiple FPGAs with Veloce proFPGA Prototyping Solution</span>
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<a href="https://link.globalspec.com/click/32747981.487221/aHR0cHM6Ly93d3cuZ2xvYmFsc3BlYy5jb20vY2xpY2svZ28yZXZlbnQ_dHlwZT1yZWdpc3RlciZldmVudElkPTQzMTkmdWlkPTM1MzUwMSZ1aD00ZjU3NWEmbWQ9MjMwOTE4Jm1oPTZBMzdCQSZjaWQ9d2ViaW5hciZldnRzcmM9U2llbWVuc0luZHVzdHJ5U29mdHdfMjMwOTI2X0ludjE/6216342320ea001fa6c452beB9d35a36c"><img src="https://www.globalspec.com/EventsPics/show4319/hero_image_url_4319.png"></a>
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<span style="font-weight:bold; font-size:16px; font-family:'Open Sans', Arial, sans-serif;"><br />Tuesday, September 26, 2023</span>
<br>
<span style="font-family:'Open Sans', Arial, sans-serif;">11:00 AM EDT / 8:00 AM PDT / 5:00 PM CEST</span>
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<span style="font-family:'Open Sans', Arial, sans-serif !important;">
What to Expect
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<p style="font-size:15px; font-family:'Open Sans', Arial, sans-serif !important;"><p>In this webinar, we will discuss the use of prototyping software, VeloceOS for Prototyping (VPS), to compile, partition and route your design, regardless of size, into FPGA prototypes with excellent performance quickly, efficiently, and automatically.</p>     
<a style="color:#767676; font-family:'Open Sans', Arial, sans-serif !important;" href="https://link.globalspec.com/click/32747981.487221/aHR0cHM6Ly93d3cuZ2xvYmFsc3BlYy5jb20vY2xpY2svZ28yZXZlbnQ_dHlwZT1yZWdpc3RlciZldmVudElkPTQzMTkmdWlkPTM1MzUwMSZ1aD00ZjU3NWEmbWQ9MjMwOTE4Jm1oPTZBMzdCQSZjaWQ9d2ViaW5hciZldnRzcmM9U2llbWVuc0luZHVzdHJ5U29mdHdfMjMwOTI2X0ludjE/6216342320ea001fa6c452beE9d35a36c">Learn more</a>.</p>
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<p style="margin:0px 0px 5px 0px; font-family:'Open Sans', Arial, sans-serif !important; font-size:13px;">SPONSORED BY</p>
<img align="center" src="https://www.globalspec.com/EventsPics/show4319/custom_event_owner_logo_url_4319.png" style="margin:0; padding:0; border:none;" border="0" alt="Siemens EDA">
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<span style="font-family:'Open Sans', Arial, sans-serif !important;">
<ul> <li>Establish an efficient approach to partitioning, routing, and multiplexing signal connectivity</li> <li>Discover how to limit schedule slips when generating prototype updates of the chip functionality</li> <li>Learn how to achieve optimal utilization of the FPGA resources and the multi-megahertz performance expected of an FPGA prototype</li> </ul>
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<span style="font-family:'Open Sans', Arial, sans-seri !importantf;">
<strong>Stephen Bailey</strong>,
<br />Director of Product Management<br />Siemens EDA
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About Siemens EDA
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<span style="font-size:13px; font-family:'Open Sans', Arial, sans-serif !important;"><p>Siemens Digital Industries Software is driving transformation to enable a digital enterprise where engineering, manufacturing and electronics design meet tomorrow. The Siemens Xcelerator portfolio helps companies of all sizes create and leverage digital twins that provide organizations with new insights, opportunities, and levels of automation to drive innovation. For more information on Siemens Digital Industries Software products and services, visit siemens.com/software or follow us on LinkedIn, Twitter, Facebook and Instagram. Siemens Digital Industries Software &#8211; Where today meets tomorrow.</p></span>
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